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19-3557; Rev 1; 4/05
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer
General Description
The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take advantage of video timing to reduce the serial data rate. The MAX9218 pairs with the MAX9217 serializer to form a complete digital video transmission system. Proprietary data decoding reduces EMI and provides DC balance. The DC balance allows AC-coupling, providing isolation between the transmitting and receiving ends of the interface. The MAX9218 features a selectable rising or falling output latch edge. ESD tolerance is specified for ISO 10605 with 10kV contact discharge and 30kV air discharge. The MAX9218 operates from a +3.3V core supply and features a separate output supply for interfacing to 1.8V to 3.3V logic-level inputs. This device is available in 48lead Thin QFN and TQFP packages and is specified from -40C to +85C.
Features
Proprietary Data Decoding for DC Balance and Reduced EMI Control Data Deserialized During Video Blanking Five Control Data Inputs Are Single Bit-Error Tolerant Output Transition Time Is Scaled to Operating Frequency for Reduced EMI Staggered Output Switching Reduces EMI Output Enable Allows Busing of Outputs Clock Pulse Stretch on Lock Wide 2% Reference Clock Tolerance Synchronizes to MAX9217 Serializer Without External Control ISO 10605 ESD Protection Separate Output Supply Allows Interface to 1.8V to 3.3V Logic +3.3V Core Power Supply Space-Saving Thin QFN and TQFP Packages -40C to +85C Operating Temperature
MAX9218
Applications
Navigation System Display In-Vehicle Entertainment System Video Camera LCD Displays
PART
Ordering Information
TEMP RANGE PIN-PACKAGE PKG CODE C48-5 T4866-1
MAX9218ECM -40C to +85C 48 TQFP MAX9218ETM -40C to +85C 48 Thin QFN-EP*
*EP = Exposed pad.
Pin Configurations
TOP VIEW RGB_OUT17 RGB_OUT16 RGB_OUT15 RGB_OUT14 RGB_OUT13 RGB_OUT12 RGB_OUT11 RGB_OUT10 RGB_OUT9 RGB_OUT8 VCCO VCCOGND RGB_OUT16 RGB_OUT15 RGB_OUT14 RGB_OUT13 RGB_OUT17 RGB_OUT12 RGB_OUT11 RGB_OUT10 RGB_OUT9 RGB_OUT8 VCCO
39 38
48
47
46
45
44
43
42
41
40
39
38
37
48
47
46
45
44
43
42
41
40
R/F RNG1 VCCLVDS IN+ INLVDS GND PLL GND VCCPLL RNG0 GND VCC REFCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
RGB_OUT7 RGB_OUT6 RGB_OUT5 RGB_OUT4 RGB_OUT3 RGB_OUT2 RGB_OUT1 RGB_OUT0 PCLK_OUT LOCK VCCO VCCOGND
37 36 35 34 33 32 31
VCCO GND
R/F RNG1 VCCLVDS IN+ INLVDS GND PLL GND VCCPLL RNG0 GND VCC REFCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
RGB_OUT7 RGB_OUT6 RGB_OUT5 RGB_OUT4 RGB_OUT3 RGB_OUT2 RGB_OUT1 RGB_OUT0 PCLK_OUT LOCK VCCO VCCO GND
MAX9218
MAX9218
30 29 28 27 26 25
PWRDWN OUTEN CNTL_OUT0 CNTL_OUT1 CNTL_OUT2 CNTL_OUT3 CNTL_OUT4 CNTL_OUT5 CNTL_OUT6 CNTL_OUT7 CNTL_OUT8 DE_OUT
CNTL_OUT5 CNTL_OUT6
CNTL_OUT0 CNTL_OUT1 CNTL_OUT2 CNTL_OUT3 CNTL_OUT4
TQFP
THIN QFN-EP
________________________________________________________________ Maxim Integrated Products
CNTL_OUT7 CNTL_OUT8 DE_OUT
PWRDWN
OUTEN
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer MAX9218
ABSOLUTE MAXIMUM RATINGS
VCC_ to _GND........................................................-0.5V to +4.0V Any Ground to Any Ground...................................-0.5V to +0.5V IN+, IN- to LVDS GND...........................................-0.5V to +4.0V IN+, IN- Short Circuit to LVDS GND or VCCLVDS ......Continuous (R/F, OUTEN, RNG_, REFCLK, PWRDWN) to GND .................................-0.5V to (VCC + 0.5V) (RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT, LOCK) to VCCO GND ...........................-0.5V to (VCCO + 0.5V) Continuous Power Dissipation (TA = +70C) 48-Lead Thin QFN (derate 37mW/C above +70C) .2963mW 48-Lead TQFP (derate 20.8mW/C above +70C) ....1667mW ESD Protection Human Body Model (RD = 1.5k, CS = 100pF) All Pins to GND...........................................................3.0kV ISO 10605 (RD = 2k, CS = 330pF) Contact Discharge (IN+, IN-) to GND ............................10kV Air Discharge (IN+, IN-) to GND ....................................30kV Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC_ = +3.0V to +3.6V, PWRDWN = high, differential input voltage VID = 0.05V to 1.2V, input common-mode voltage VCM = VID/2 to VCC - VID/2, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC_ = +3.3V, VID = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 1, 2)
PARAMETER High-Level Input Voltage Low-Level Input Voltage Input Current Input Clamp Voltage SYMBOL VIH VIL IIN VCL VIN = -0.3V to (VCC + 0.3V), PWRDWN = high or low ICL = -18mA IOH = -100A High-Level Output Voltage VOH IOH = -2mA, RNG1, RNG0 = high IOH = -2mA, RNG1, RNG0 both not high simultaneously IOL = 100A Low-Level Output Voltage VOL IOL = 2mA, RNG1, RNG0 = high IOL = 2mA, RNG1, RNG0 both not high simultaneously High-Impedance Output Current IOZ PWRDWN = low or OUTEN = low, VO = -0.3V to VCCO + 0.3V -10 VCCO - 0.1 VCCO - 0.35 VCCO - 0.4 0.1 0.3 0.35 +10 A V V CONDITIONS MIN 2.0 -0.3 -70 TYP MAX VCC + 0.3 +0.8 +70 -1.5 UNITS V V A V
SINGLE-ENDED INPUTS (R/F, OUTEN, RNG0, RNG1, REFCLK, PWRDWN)
SINGLE-ENDED OUTPUTS (RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT, LOCK)
2
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27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC_ = +3.0V to +3.6V, PWRDWN = high, differential input voltage VID = 0.05V to 1.2V, input common-mode voltage VCM = VID/2 to VCC - VID/2, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC_ = +3.3V, VID = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 1, 2)
PARAMETER Output Short-Circuit Current LVDS INPUT (IN+, IN-) Differential Input High Threshold Differential Input Low Threshold Input Current Input Bias Resistor VTH VTL IIN+, IINRIB PWRDWN = high or low PWRDWN = high or low VCC_ = 0 or open, PWRDWN = 0 or open, Figure 1 VCC_ = 0 or open, PWRDWN = 0 or open 3MHz 7MHz 7MHz 15MHz 15MHz 35MHz -50 -20 35 35 -40 50 50 +20 65 65 +40 50 mV mV A k k A SYMBOL IOS CONDITIONS RNG1, RNG0 = high, VO = 0 RNG1, RNG0 both not high simultaneously, VO = 0 MIN -10 -7 TYP MAX -50 -40 mA UNITS
MAX9218
Power-Off Input Current POWER SUPPLY
IINO+, IINO-
Worst-Case Supply Current
ICCW
CL = 8pF, worst-case pattern, Figure 2
RNG1 = low, RNG0 = low RNG1 = high, RNG0 = low RNG1 = high, RNG0 = high
20 35 25 47 37 70 50 A mA
Power-Down Supply Current
ICCZ
(Note 3)
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3
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer MAX9218
AC ELECTRICAL CHARACTERISTICS
(VCC_ = +3.0V to 3.6V, CL = 8pF, PWRDWN = high, differential input voltage VID = 0.1V to 1.2V, input common-mode voltage VCM = VID/2 to VCC - VID/2, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC_ = +3.3V, VID = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 4, 5)
PARAMETER REFCLK TIMING REQUIREMENTS Period Frequency Frequency Variation Duty Cycle Transition Time SWITCHING CHARACTERISTICS RNG1, RNG0 = high Output Rise Time tR Figure 3 RNG1, RNG0 both not high simultaneously RNG1, RNG0 = high Output Fall Time tF Figure 3 RNG1, RNG0 both not high simultaneously 3.2 3.8 2.7 3.6 0.4 x tT 0.4 x tT 0.35 x tT 0.35 x tT 2.575 x tT + 8.5 0.45 x tT 0.45 x tT 0.4 x tT 0.4 x tT 2.725 x tT + 12.8 16385 x tT 100 30 30 4.4 5.5 4.5 5.3 0.6 x tT 0.6 x tT ns ns tT fCLK fCLK DC tTRAN 20% to 80% REFCLK to serializer PCLK_IN 28.57 3 -2.0 40 50 333.00 35 +2.0 60 6 ns MHz % % ns SYMBOL CONDITIONS MIN TYP MAX UNITS
PCLK_OUT High Time PCLK_OUT Low Time Data Valid Before PCLK_OUT Data Valid After PCLK_OUT Input-to-Output Delay
tHIGH tLOW tDVB tDVA tDELAY
Figure 4 Figure 4 Figure 5 Figure 5 Figure 6
ns ns ns ns ns
PLL Lock to REFCLK Power-Down Delay Output Enable Time Output Disable Time
tPLLREF tPDD tOE tOZ
Figure 7 Figure 7 Figure 8 Figure 9
ns ns ns ns
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH and VTL. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25C. Note 3: All LVTTL/LVCMOS inputs, except PWRDWN at 0.3V or VCC - 0.3V. PWRDWN is 0.3V. Note 4: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at 6 sigma. Note 5: CL includes probe and test jig capacitance.
4
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27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer
Typical Operating Characteristics
(VCC_ = +3.3V, CL = 8pF, TA = +25C, unless otherwise noted.)
MAX9218
WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY
MAX9218 toc01
OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO)
6 5 4 3 2 1 RNG1 = RNG0 = HIGH 0 tF tR
MAX9218 toc02
80 70 SUPPLY CURRENT (mA) 60 50 40 30 20 10 0 3 7 11 15 19 23 27 31
7 OUTPUT TRANSITION TIME (ns)
35
1.8
2.1
2.4
2.7
3.0
3.3
FREQUENCY (MHz)
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO)
MAX9218 toc03
BIT-ERROR RATE vs. CABLE LENGTH
CAT5e 10 -13
MAX9218 toc04
7 OUTPUT TRANSITION TIME (ns) 6 5 4 3 2 1 RNG1 = RNG0 = BOTH NOT HIGH 0 1.8 2.1 2.4 2.7 3.0 tF tR
10 -14
BIT-ERROR RATE
10 -12
10 -11 35MHz CLOCK 700Mbps DATA RATE FOR <12m, BER < 10-12 0 4 8 12 16 20
10 -10 3.3 OUTPUT SUPPLY VOLTAGE (V)
CAT5e CABLE LENGTH (m)
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5
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer MAX9218
Pin Description
PIN 1 NAME R/F FUNCTION Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT for latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a falling latch edge. Internally pulled down to GND. LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input frequency. Internally pulled down to GND. LVDS Supply Voltage. Bypass to LVDS GND with 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. Noninverting LVDS Serial Data Input Inverting LVDS Serial Data Input LVDS Supply Ground PLL Supply Ground PLL Supply Voltage. Bypass to PLL GND with 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input frequency. Internal pulldown to GND. Digital Supply Ground Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to GND with 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. LVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within 2% of the serializer PCLK_IN frequency. Internally pulled down to GND. LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. LVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs. Driving low places the single-ended outputs in high impedance. Internally pulled down to GND. LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:0] are latched into the next chip on the rising or falling edge of PCLK_OUT as selected by R/F when DE_OUT is low, and are held at the last state when DE_OUT is high. LVTTL/LVCMOS Data Enable Output. High indicates RGB_OUT[17:0] are active. Low indicates CNTL_OUT[8:0] are active. Output Supply Ground Output Supply Voltage. Bypass to GND with 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. LVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low. LVTTL/LVCMOS Parallel Clock Output. Latches data into the next chip on the edge selected by R/F. LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Outputs. RGB_OUT[17:0] are latched into the next chip on the edge of PCLK_OUT selected by R/F when DE_OUT is high, and are held at the last state when DE_OUT is low. Exposed Pad for Thin QFN Package Only. Connect to GND.
2 3 4 5 6 7 8 9 10 11
RNG1 VCCLVDS IN+ INLVDS GND PLL GND VCCPLL RNG0 GND VCC
12 13 14
REFCLK PWRDWN OUTEN
15-23
CNTL_OUT [8:0]
24 25, 37 26, 38 27 28 29-36, 39-48 EP
DE_OUT VCCO GND VCCO LOCK PCLK_OUT RGB_OUT [17:0] GND
6
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27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer
Functional Diagram
R/F OUTEN RGB_OUT[17:0] CNTL_OUT[8:0] DE_OUT RNG0 RNG1 PCLK_OUT PLL REFCLK TIMING AND CONTROL PWRDWN LOCK
MAX9218
IN+ INDC BALANCE/ DECODE SER-TO-PAR
1 0
MAX9218
IN+ RIB 1.2V LVDS RECEIVER DE_OUT LOCK PCLK_OUT RGB_OUT[17:0] RIB INCNTL_OUT[8:0] tR tF 0.1VCCO 0.9VCCO
Figure 1. LVDS Input Bias
Figure 3. Output Rise and Fall Times
PCLK_OUT
PCLK_OUT 2.0V ODD RGB_OUT CNTL_OUT EVEN RGB_OUT CNTL_OUT tLOW tHIGH 0.8V
RISING LATCH EDGE SHOWN (R/F = HIGH).
Figure 2. Worst-Case Output Pattern
Figure 4. High and Low Times
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7
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer MAX9218
PCLK_OUT 0.8V 2.0V
PCLK_OUT SHOWN FOR R/F = HIGH (RISING LATCH EDGE) tDVB DE_OUT LOCK RGB_OUT[17:0] CNTL_OUT[8:0] 2.0V 0.8V 2.0V 0.8V tDVA
Figure 5. Synchronous Output Timing
20 SERIAL BITS
PCLK_OUT SHOWN FOR R/F = HIGH
IN+, IN-
SERIAL-WORD N
SERIAL-WORD N + 1
tDELAY
PCLK_OUT
CNTL_OUT RGB_OUT
PARALLEL-WORD N - 1
PARALLEL-WORD N
Figure 6. Deserializer Delay
8
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27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer MAX9218
2.0V PWRDWN 0.8V tPLLREF TRANSITION WORD FOUND tPDD
REFCLK
RECOVERED CLOCK PCLK_OUT HIGH IMPEDANCE HIGH IMPEDANCE
CLOCK STRETCH RGB_OUT CNTL_OUT DE_OUT HIGH IMPEDANCE
VALID DATA HIGH IMPEDANCE
LOCK
HIGH IMPEDANCE
HIGH IMPEDANCE
NOTE: R/F = HIGH
Figure 7. PLL Lock to REFCLK and Power-Down Delay
OUTEN 0.8V tOE DE_OUT LOCK RGB_OUT[17:0] CNTL_OUT[8:0] HIGH-Z ACTIVE
OUTEN
2.0V
tOZ DE_OUT LOCK RGB_OUT[17:0] CNTL_OUT[8:0] ACTIVE HIGH-Z
Figure 8. Output Enable Time
Figure 9. Output Disable Time
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9
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer MAX9218
Detailed Description
The MAX9218 DC-balanced deserializer operates at a parallel clock frequency of 3MHz to 35MHz, deserializing video data to the RGB_OUT[17:0] outputs when the data enable output DE_OUT is high, or control data to the CNTL_OUT[8:0] outputs when DE_OUT is low. The video phase words are decoded using 2 overhead bits, EN0 and EN1. Control phase words are decoded with 1 overhead bit, EN0. Encoding, performed by the MAX9217 serializer, reduces EMI and maintains DC balance across the serial cable. The serial input word formats are shown in Table 1 and Table 2. Control data inputs C0 to C4, each repeated over 3 serial bit times by the serializer, are decoded using majority voting. Two or three bits at the same state determine the state of the recovered bit, providing single bit-error tolerance for C0 to C4. The state of C5 to C8 is determined by the level of the bit itself (no voting is used).
Applications Information
Selection of AC-Coupling Capacitors
See Figure 12 for calculating the capacitor values for AC-coupling, depending on the parallel clock frequency. The plot shows capacitor values for two- and fourcapacitor-per-link systems. For applications using less than 18MHz clock frequency, use 0.125F capacitors.
Termination and Input Bias
The IN+ and IN- LVDS inputs are internally connected to +1.2V through 35k (min) to provide biasing for ACcoupling (Figure 1). Assuming 100 interconnect, the LVDS input can be terminated with a 100 resistor. Match the termination to the differential impedance of the interconnect. Use a Thevenin termination, providing 1.2V bias, on an AC-coupled link in noisy environments. For interconnect with 100 differential impedance, pull each LVDS line up to VCC with 130 and down to ground with 82 at the deserializer input (Figure 10 and Figure 11). This termination provides both differential and commonmode termination. The impedance of the Thevenin termination should be half the differential impedance of the interconnect and provide a bias voltage of 1.2V.
AC-Coupling Benefits
AC-coupling increases the input voltage of the LVDS receiver to the voltage rating of the capacitor. Two capacitors are sufficient for isolation, but four capacitors--two at the serializer output and two at the deserializer input--provide protection if either end of the cable is shorted to a high voltage. AC-coupling blocks low-frequency ground shifts and common-mode noise. The MAX9217 serializer can also be DC-coupled to the MAX9218 deserializer. Figure 10 is the AC-coupled serializer and deserializer with two capacitors per link, and Figure 11 is the AC-coupled serializer and deserializer with four capacitors per link.
Table 1. Serial Video Phase Word Format
0 EN0 1 EN1 2 S0 3 S1 4 S2 5 S3 6 S4 7 S5 8 S6 9 S7 10 S8 11 S9 12 S10 13 S11 14 S12 15 S13 16 S14 17 S15 18 S16 19 S17
Bit 0 is the LSB and is deserialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.
Table 2. Serial Control Phase Word Format
0 EN0 1 C0 2 C0 3 C0 4 C1 5 C1 6 C1 7 C2 8 C2 9 C2 10 C3 11 C3 12 C3 13 C4 14 C4 15 C4 16 C5 17 C6 18 C7 19 C8
Bit 0 is the LSB and is deserialized first. C[8:0] are the mapped control inputs.
10
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27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer MAX9218
VCC 130 DC BALANCE/ ENCODE INPUT LATCH PAR-TO-SER * OUT * 82 82 IN RGB_IN CNTL_IN DE_IN 130 DC BALANCE/ DECODE SER-TO-PAR 1 0
1 0
R/F OUTEN RGB_OUT CNTL_OUT DE_OUT
CMF
RNG0 PCLK_IN RNG0 RNG1 PWRDWN PLL TIMING AND CONTROL MOD0 MOD1 RNG1
PCLK_OUT PLL REF_IN TIMING AND CONTROL PWRDWN LOCK
MAX9217
MAX9218
CERAMIC RF SURFACE-MOUNT CAPACITOR
100 DIFFERENTIAL STP CABLE
*CAPS CAN BE AT EITHER END.
Figure 10. AC-Coupled Serializer and Deserializer with Two Capacitors per Link
VCC 130 DC BALANCE/ ENCODE INPUT LATCH PAR-TO-SER RGB_IN CNTL_IN DE_IN 1 0 130 DC BALANCE/ DECODE SER-TO-PAR 1 0
R/F OUTEN RGB_OUT CNTL_OUT DE_OUT
OUT 82 82
IN
CMF
RNG0 PCLK_IN RNG0 RNG1 PWRDWN PLL TIMING AND CONTROL MOD0 MOD1 RNG1
PCLK_OUT PLL REF_IN TIMING AND CONTROL PWRDWN LOCK
MAX9217
MAX9218
CERAMIC RF SURFACE-MOUNT CAPACITOR
100 DIFFERENTIAL STP CABLE
Figure 11. AC-Coupled Serializer and Deserializer with Four Capacitors per Link ______________________________________________________________________________________ 11
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer MAX9218
Input Frequency Detection
A frequency-detection circuit detects when the LVDS input is not switching. When not switching, all outputs except LOCK are low, LOCK is high, and PCLK_OUT follows REFCLK. This condition occurs, for example, if the serializer is not driving the interconnect or if the interconnect is open.
AC-COUPLING CAPACITOR VALUE vs. PARALLEL CLOCK FREQUENCY
140 125 CAPACITOR VALUE (nF) 110 95 80 65 50 35 20 18 21 24 27 30 33 36 PARALLEL CLOCK FREQUENCY (MHz) TWO CAPACITORS PER LINK FOUR CAPACITORS PER LINK
Frequency Range Setting (RNG[1:0])
The RNG[1:0] inputs select the operating frequency range of the MAX9218 and the transition time of the outputs. Select the frequency range that includes the MAX9217 serializer PCLK_IN frequency. Table 3 shows the selectable frequency ranges and the corresponding data rates and output transition times.
Power Down
Driving PWRDWN low puts the outputs in high impedance and stops the PLL. With PWRDWN 0.3V and all LVTTL/LVCMOS inputs 0.3V or VCC - 0.3V, the supply current is reduced to less than 50A. Driving PWRDWN high initiates lock to the local reference clock (REFCLK) and afterwards to the serial input.
Figure 12. AC-Coupling Capacitor Values vs. Clock Frequency of 18MHz to 35MHz
Lock and Loss of Lock (LOCK)
When PWRDWN is driven high, the PLL begins locking to REFCLK, drives LOCK from high impedance to high and the other outputs from high impedance to low except PCLK_OUT. PCLK_OUT outputs REFCLK while the PLL is locking to REFCLK. Locking to REFCLK takes a maximum of 16,385 REFCLK cycles. When locking to REFCLK is complete, the serial input is monitored for a transition word. When a transition word is found, LOCK is driven low indicating valid output data, and the parallel rate clock recovered from the serial input is output on PCLK_OUT. PCLK_OUT is stretched on the change from REFCLK to recovered clock (or vice versa).
If a transition word is not detected within 220 cycles of PCLK_OUT, LOCK is driven high and the other outputs except PCLK_OUT are driven low. REFCLK is output on PCLK_OUT and the deserializer continues monitoring the serial input for a transition word. See Figure 7 for the synchronization timing diagram.
Output Enable (OUTEN) and Busing Outputs
The outputs of two MAX9218s can be bused to form a 2:1 mux with the outputs controlled by the output enable. Wait 30ns between disabling one deserializer (driving OUTEN low) and enabling the second one (driving OUTEN high) to avoid contention of the bused outputs. OUTEN controls all outputs.
Rising or Falling Output Latch Edge (R/F)
The MAX9218 has a selectable rising or falling output latch edge through a logic setting on R/F. Driving R/F high selects the rising output latch edge, which latches the parallel output data into the next chip on the rising edge of PCLK_OUT. Driving R/F low selects the falling output latch edge, which latches the parallel output data into the next chip on the falling edge of PCLK_OUT. The MAX9218 output-latch-edge polarity does not need to match the MAX9217 serializer inputlatch-edge polarity. Select the latch-edge polarity required by the chip being driven by the MAX9218.
Table 3. Frequency Range Programming
RNG1 0 0 1 1 RNG0 0 1 0 1 PARALLEL CLOCK (MHz) 3 to 7 7 to 15 15 to 35 SERIAL DATA RATE (Mbps) 60 to 140 140 to 300 300 to 700 Fast OUTPUT TRANSITION TIME
Slow
12
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27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer
Staggered and Transition Time Adjusted Outputs
RGB_OUT[17:0] are grouped into three groups of six, with each group switching about 1ns apart in the video phase to reduce EMI and ground bounce. CNTL_OUT[8:0] switch during the control phase. Output transition times are slower in the 3MHz-to-7MHz and 7MHz-to-15MHz ranges and faster in the 15MHz-to35MHz range. (VCCLVDS supply and VCCLVDS GND). The grounds are isolated by diode connections. Bypass each V CC , VCCO, VCCPLL, and VCCLVDS pin with high-frequency, surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. The outputs are powered from V CCO , which accepts a 1.71V to 3.6V supply, allowing direct interface to inputs with 1.8V to 3.3V logic levels.
MAX9218
Data Enable Output (DE_OUT)
The MAX9218 deserializes video and control data at different times. Control data is deserialized during the video blanking time. DE_OUT high indicates that video data is being deserialized and output on RGB_OUT[17:0]. DE_OUT low indicates that control data is being deserialized and output on CNTL_OUT[8:0]. When outputs are not being updated, the last data received is latched on the outputs. Figure 13 shows the DE_OUT timing.
Cables and Connectors
Interconnect for LVDS typically has a differential impedance of 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
Power-Supply Circuits and Bypassing
There are separate on-chip power domains for digital circuits and LVTTL/LVCMOS inputs (VCC supply and GND), outputs (V CCO supply and V CCO GND), PLL (VCCPLL supply and VCCPLL GND), and the LVDS input
Board Layout
Separate the LVTTL/LVCMOS outputs and LVDS inputs to prevent crosstalk. A four-layer PC board with separate layers for power, ground, and signals is recommended.
CONTROL DATA
VIDEO DATA
CONTROL DATA
PCLK_OUT
CNTL_OUT
DE_OUT
RGB_OUT
PCLK_OUT TIMING SHOWN FOR R/F = HIGH (RISING OUTPUT LATCH EDGE) = OUTPUT DATA HELD
Figure 13. Output Timing ______________________________________________________________________________________ 13
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer MAX9218
ESD Protection
The MAX9218 ESD tolerance is rated for the Human Body Model and ISO 10605. ISO 10605 specifies ESD tolerance for electronic systems. The Human Body Model discharge components are CS = 100pF and RD = 1.5k (Figure 14). The ISO 10605 discharge components are CS = 330pF and RD = 2k (Figure 15).
1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF
RD 1.5k DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE
50 TO 100 CHARGE-CURRENTLIMIT RESISTOR CS 330pF
RD 2k DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
Figure 14. Human Body ESD Test Circuit
Figure 15. ISO 10605 Contact Discharge ESD Test Circuit
Chip Information
TRANSISTOR COUNT: 17,782 PROCESS: CMOS
14
______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
32L/48L,TQFP.EPS
MAX9218
PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm
21-0054
E
1
2
PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm
21-0054
E
2
2
______________________________________________________________________________________
15
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer MAX9218
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
48L THIN QFN.EPS
PACKAGE OUTLINE, 48L THIN QFN 6x6x0.8mm BODY / 0.4mm LEAD PITCH
21-0160
A
1
2
NOTE : 1. ALL DIMENSIONS ARE IN mm. ANGLES IN DEGREES. 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. COPLANARITY SHALL NOT EXCEED 0.08mm. 3. WARPAGE SHALL NOT EXCEED 0.10 mm. 4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC. (S) 5. REFER TO JEDEC MO-220. 6. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 7. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
COMMON DIMENSIONS
SYMBOLS
EXPOSED PAD VARIATONS MAX.
0.800 0.050 0.250 6.100 6.050 0.450 0.550 0.600 0.500
PKG. CODE
MIN.
0.700 0.000 0.150 5.900 5.900 0.250 0.350 0.400 0.300
NOM.
0.750 -- -0.200 REF. 0.200 6.000 0.400 TYP. 6.000 0.350 0.450 0.500 0.400 48 12 12
D2
MIN. 4.20 NOM. 4.30 MAX. 4.40 MIN. 4.20
E2
NOM. 4.30 MAX. 4.40
A A1 A2 b D e E k k1 L L1 N ND NE
T4866-1
PACKAGE OUTLINE, 48L THIN QFN 6x6x0.8mm BODY / 0.4mm LEAD PITCH
21-0160
A
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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